
PIC18FXX39
DS30485A-page 146
Preliminary
2002 Microchip Technology Inc.
FIGURE 16-13:
I2C SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)
SDA
SCL
SS
PI
F
BF
(
S
SPS
TA
T
<
0
>
)
SSP
O
V
(
S
SPCO
N
<
6>
)
S
1
2
3
4
56
7
8
9
1
23
4
5
6
7
89
1
2
3
4
5
7
8
9
P
A
7
A6
A
5
A4
A
3
A2
A
1
D7
D6
D5
D4
D3
D
2
D1
D0
D7
D6
D5
D4
D3
D1
D0
ACK
Re
ce
ivin
gDa
ta
ACK
Re
ce
ivin
gDa
ta
R/W
=
0
ACK
R
e
cei
vi
ng
A
ddr
ess
Cle
a
re
d
in
so
ftwa
re
SSP
BUF
is
re
a
d
B
u
sM
a
st
er
ter
m
inate
s
tra
n
sfer
S
SPO
V
is
se
t
b
e
ca
us
e
SS
PBU
F
is
still
fu
ll.
ACK
is
n
o
tsent
.
D2
6
(P
IR
1<
3>
)
CK
P
CK
P
wr
itte
n
to
‘1
’in
If
B
F
is
cleare
d
pr
ior
to
the
fa
llin
g
edg
e
of
the
9th
cl
ock,
CKP
will
n
ot
b
e
r
e
se
t
to
‘0
’and
n
o
clock
str
e
tch
in
g
will
o
ccu
r
softwar
e
Clo
ck
is
h
e
ld
lo
w
u
n
til
CK
P
is
set
to
‘1’
Clo
ck
is
n
o
th
e
ld
lo
w
be
cause
b
u
ffer
ful
lbi
ti
s
cl
ear
pr
io
rto
fal
ling
ed
ge
of
9th
cl
ock
Clo
ck
is
n
o
th
e
ld
lo
w
becau
se
A
C
K
=
1
BF
is
se
ta
fte
r
fa
llin
g
edge
o
fthe
9
th
cl
ock,
CKP
is
r
e
se
tto
‘0
’a
nd
clock
str
e
tch
ing
occu
rs